Nonvolatile memory circuits such as electrically erasable programmable read only memories (EEPROM) and Flash EEPROMs have been widely used for several decades in various circuit applications including computer memory, automotive applications, and video games. Many new applications, however, require the access time and packing density of previous generation nonvolatile memories in addition to low power consumption for battery powered circuits. One nonvolatile memory technology that is particularly attractive for these low power applications is the ferroelectric memory cell. A major advantage of these ferroelectric memory cells is that they require approximately three orders of magnitude less energy for write operations than previous generation floating gate memories. Furthermore, they do not require high voltage power supplies for programming and erasing charge stored on a floating gate. Thus, circuit complexity is reduced and reliability increased.
The term ferroelectric is something of a misnomer, since present ferroelectric capacitors contain no ferrous material. Typical ferroelectric capacitors include a dielectric of ferroelectric material formed between two closely-spaced conducting plates. One well-established family of ferroelectric materials known as perovskites has a general formula ABO3. This family includes Lead Zirconate Titanate (PZT) having a formula Pb(ZrxTi1-x) O3. This material is a dielectric with a desirable characteristic that a suitable electric field will displace a central atom of the lattice. This displaced central atom, either Titanium or Zirconium, remains displaced after the electric field is removed, thereby storing a net charge. Another family of ferroelectric materials is Strontium Bismuth Titanate (SBT) having a formula SbBi2Ta2O9. SBT has several advantages over PZT. However, both ferroelectric materials suffer from fatigue and imprint. Fatigue is characterized by a gradual decrease in net stored charge with repeated cycling of a ferroelectric capacitor. Imprint is a tendency to prefer one state over another if the ferroelectric capacitor remains in that state for a long time as will be discussed in detail. Both fatigue and imprint as well as normal process variations may result in a weak “1” or a weak “0” having less than nominal stored net charge.
A typical one-transistor, one-capacitor (1T1C) ferroelectric memory cell of the prior art is illustrated at FIG. 1. The ferroelectric memory cell is similar to a 1T1C dynamic random access memory (DRAM) cell except for ferroelectric capacitor 100. The ferroelectric capacitor 100 is connected between plateline 110 and storage node 112. Access transistor 102 has a current path connected between bitline 108 and storage node 112. A control gate of access transistor 102 is connected to wordline 106 to control reading and writing of data to the ferroelectric memory cell. This data is stored as a polarized charge corresponding to cell voltage VCAP. Capacitance of bitline BL is represented by capacitor CBL 104.
Referring to FIG. 2, there is a hysteresis curve corresponding to the ferroelectric capacitor 100. The hysteresis curve includes net charge Q or polarization along the vertical axis and applied voltage along the horizontal axis. By convention, the polarity of the ferroelectric capacitor voltage is defined as shown in FIG. 1. A stored “0”, therefore, is characterized by a positive voltage at the plateline terminal with respect to the access transistor terminal. A stored “1” is characterized by a negative voltage at the plateline terminal with respect to the access transistor terminal. A “0” is stored in a write operation by applying a voltage Vmax across the ferroelectric capacitor. This stores a saturation charge Qs in the ferroelectric capacitor. The ferroelectric capacitor, however, includes a linear component in parallel with a switching component. When the electric field is removed, therefore, the linear component discharges and only the residual charge Qr remains in the switching component. The stored “0” is rewritten as a “1” by applying −Vmax to the ferroelectric capacitor. This charges the linear and switching components of the ferroelectric capacitor to a saturation charge of −Qs. The stored charge reverts to −Qr when the voltage across the ferroelectric capacitor is removed. Finally, coercive points VC and −VC are minimum voltages on the hysteresis curve that will degrade a stored data state. For example, application of VC across a ferroelectric capacitor will degrade a stored “1” even though it is not sufficient to store a “0”. Thus, it is particularly important to avoid voltages near these coercive points unless the ferroelectric capacitor is being accessed.
Referring to FIG. 3, there is illustrated a typical write sequence for a ferroelectric memory cell as in FIG. 1. Initially, the bitline (BL), wordline (WL), and plateline (PL) are all low. The upper row of hysteresis curves illustrates a write “1” and the lower row represents a write “0”. Either a “1” or “0” is initially stored in each exemplary memory cell. The write “1” is performed when the bitline BL and wordline WL are high and the plateline PL is low. This places a negative voltage across the ferroelectric capacitor and charges it to −Qs. When plateline PL goes high, the voltage across the ferroelectric capacitor is 0 V, and the stored charge reverts to −Qr. At the end of the write cycle, both bitline BL and plateline PL go low and stored charge −Qr remains on the ferroelectric capacitor. Alternatively, the write “0” occurs when bitline BL remains low and plateline PL goes high. This places a positive voltage across the ferroelectric capacitor and charges it to Qs representing a stored “0”. When plateline PL goes low, the voltage across the ferroelectric capacitor is 0 V, and the stored charge reverts to Qr representing a stored “0”.
A read operation is illustrated at FIG. 4 for the ferroelectric memory cell at FIG. 1. The upper row of hysteresis curves illustrates a read “0”. The lower row of hysteresis curves illustrates a read “1”. Wordline WL and plateline PL are initially low. Bitlines BL are precharged low. At time Δt0 bitline precharge signal PRE goes low, permitting the bitlines BL to float. At time Δt1 both wordline WL and plateline PL go high, thereby permitting each memory cell to share charge with a respective bitline. A stored “1” will share more charge with parasitic bitline capacitance CBL and produce a greater bitline voltage than the stored “0” as shown. A reference voltage (FIG. 6) is produced at each complementary bitline of an accessed bitline. This reference voltage is between the “1” and “0” voltages. Sense amplifiers are activated at the time boundary between Δt1 and Δt2. When respective bitline voltages are fully amplified in time Δt2, the read “0” curve cell charge has increased from Qr to Qs. By way of comparison, the read “1” data state has changed from a stored “1” to a stored “0”. Thus, the read “0” operation is nondestructive, but the read “1” operation is destructive. At time Δt3, plateline PL goes low and applies −Vmax to the read “1” cell, thereby storing −Qs. At the same time, zero voltage is applied to the read “0” cell and charge Qr is restored. At the end of time Δt3, signal PRE goes high and precharges both bitlines BL to zero volts or ground. Thus, zero volts is applied to the read “1” cell and −Qr is restored.
Referring to FIGS. 5A and 5B, there are timing diagrams illustrating two different types of sensing that may be used in ferroelectric memory circuits. A primary difference between these two schemes is that the step sensing scheme (FIG. 5A) uses a single pulse of plateline PL, while the pulse sensing scheme (FIG. 5B) uses a double pulse of plateline PL. For both types of sensing, bitline precharge signal PRE goes low at time t0, thereby permitting the bitlines BL to float. Next, wordline WL goes high at time t1 to turn on access transistors of a row of memory cells. Plateline PL goes high between times t1 and t2, permitting ferroelectric memory cells share charge with their respective bitlines BL and develop respective difference voltages. Here, V1 represents a data “1” and V0 represents a data “0”. The difference voltage available for sensing is the difference between one of V1 and V0 and a reference voltage (FIG. 6) which lies approximately midway between voltages V1 and V0. This difference voltage is amplified at time t3 for the step sensing scheme (FIG. 5A) so that full bitline BL voltages are developed before the plateline PL goes low at time t4. The data “0” cell is fully restored between time t3 and time t4 while plateline PL is high and the data “0” bitline BL is low. At time t4, the plateline PL goes low while the data “1” bitline BL remains high. Thus, the data “1” cell is restored between time t4 and time t5. Bitline precharge signal PRE goes high at time t5, thereby precharging the bitlines BL to ground or 0 V. The step sensing cycle is completed when wordline WL goes low at time t6 to store respective data in the row of memory cells.
Referring now to FIG. 5B, the first pulse of plateline PL develops a difference voltage at time t2. Plateline PL then goes low at time t3, and the common mode difference voltage goes to near 0 V. Then the difference voltage is amplified at time t4, and full bitline BL voltages are developed while the plateline PL is low. Thus, the data “1” cell is restored between time t4 and time t5 while plateline PL is low and the data “1” bitline BL is high. At time t5, the plateline PL goes high while the data “0” bitline BL remains low. Thus, the data “0” cell is restored between time t5 and time t6. The data “1” cell is again restored between time t6 and time t7 while plateline PL is low and the data “1” bitline BL is high. Bitline precharge signal PRE goes high at time t7, thereby precharging the bitlines BL to ground or 0V. The pulse sensing cycle is completed when wordline WL goes low at time t8.